Logic Gates

Introduction

Logic gates serve as the building blocks to digital logic circuits using combinational logic. We're going to consider the following gates: NOT gates (also called inverters), AND gates, OR gates, NAND gates, NOR gates, XOR gates, and XNOR gates. We'll also discuss the concept of gate deltay.

NOT gates

NOT gates or inverters have a single bit input and a single bit of output. This is a diagram of a NOT gate. It is a triangle with a circle on the right. The circle indicates "negation".
The truth table defines the behavior of this gate.

x	z
0	1
1	0

where x is the input and z is the output.

AND₂ gates

AND₂ gates have two bits of input and a single bit of output. The subscript, 2, indicates how many inputs this AND gate has. For example, AND₃ gates have 3 inputs. The output of AND₂ gate is 1 only if both inputs are 1. Otherwise, the output is 0.
The truth table defines the behavior of this gate.

x1	x0	z
0	0	0
0	1	0
1	0	0
1	1	1

The function implmented by AND₂ gates has interesting properties:

• The function is symmetric. Thus, x * y == y * x. This can be verified by using truth tables. We use * to represent AND₂.
• The function is associative. Thus, (x * y) * z == x * (y * z). This can be verified by using truth tables.

Because of these properties, it's easy to define AND_n, which is an n-input AND gate. AND_n(x₁, x₂,...,x_n) = x₁ * x₂ * ... * x_n That is, an AND gate with n-inputs is the AND of all the bits. This is not ambiguous because the AND function is associative (all parenthesization of this expression are equivalent).

OR₂ gates

OR₂ gates have two bits of input and a single bit of output. The subscript, 2, indicates how many inputs this OR gate has. For example, OR₃ gates have 3 inputs. The output of OR₂ gate is 0 only if both inputs are 0. Otherwise, the output is 1.
The truth table defines the behavior of this gate.

x1	x0	z
0	0	0
0	1	1
1	0	1
1	1	1

The function implemented by OR₂ gates has interesting properties:

• The function is symmetric. Thus, x + y == y + x. This can be verified by using truth tables. We use "+" to represent OR₂
• The function is associative. Thus, (x + y) + z == x + (y + z). This can be verified by using truth tables.

Because of these properties, it's easy to define OR_n, which is an n-input OR gate. OR_n(x₁, x₂,...,x_n) = x₁ + x₂ + ... + x_n That is, an AND gate with n-inputs is the AND of all the bits. This is not ambiguous because the AND function is associative (all parenthesization of this expression are equivalent).

NAND₂ gates

NAND₂ gates have two bits of input and a single bit of output. The subscript, 2, indicates how many inputs this NAND gate has. For example, NAND₃ gates have 3 inputs. NAND_k gates is define unusually. Since NAND₂ is not associative, the definition is based on AND₂.
In particular
NAND_k(x₁, x₂,...,x_n) = NOT( AND_k(x₁, x₂,...,x_n) ) Thus, NAND_k is the negation of AND_k.
The truth table defines the behavior of this gate. It's the negation of AND₂.

x1	x0	z
0	0	1
0	1	1
1	0	1
1	1	0

The function implemented by NAND₂ gates has interesting properties:

• The function is symmetric. Thus, x NAND y == y NAND x. This can be verified by using truth tables.
• The function is not associative. This can be verified by using truth tables.

Because of these properties, NAND_k is defined from AND_k, and not built from NAND₂ gates.

NOR₂ gates

OR₂ gates have two bits of input and a single bit of output. The subscript, 2, indicates how many inputs this OR gate has. For example, NOR₃ gates have 3 inputs. The output of NOR₂ gate is the negation of OR₂.
The truth table defines the behavior of this gate.

x1	x0	z
0	0	1
0	1	0
1	0	0
1	1	0

The function implmented by NOR₂ gates has interesting properties:

• The function is symmetric. Thus, x NOR y == y NOR x. This can be verified by using truth tables.
• The function is not associative. This can be verified by using truth tables.

Because of these properties, NOR_k is defined from OR_k, and not built from NOR₂ gates.

XOR₂ gates

XOR₂ gates have two bits of input and a single bit of output. The output of XOR₂ gate is 1 only if the inputs have opposite values. That is, when one input has value 0, and the other has value 1.. Otherwise, the output is 0.
This is called exclusive-or. The definition of OR₂ is inclusive-or, where the output is 1 if either input is 1, or if both inputs are 1.
XOR₂ can be defined using AND₂, OR₂, and NOT.
x XOR y == ( x AND (NOT y) ) OR ( (NOT x) AND y ) == x\y + y\x
Here's a diagram of the XOR₂ gate.

If you look carefully at the drawing of the gate, there is a second arc behind the first one near the inputs. Since this second arc is hard to see, it's usually a good idea to write the word "XOR" inside the gate.
The truth table defines the behavior of this gate.

x1	x0	z
0	0	0
0	1	1
1	0	1
1	1	0

The function implmented by XOR₂ gates has interesting properties:

• The function is symmetric. Thus, x (+) y == y (+) x. This can be verified by using truth tables. (We use (+) to denote logical XOR--ideally, we'd draw it with a + sign inside a circle, but HTML doesn't seem to have a symbol for this).
• The function is associative. Thus, [ x (+) y ] (+) z == x (+) [ y (+) z ]. This can be verified by using truth tables.

Because of these properties, it's easy to define XOR_n, which is an n-input XOR gate. XOR_n(x₁, x₂,...,x_n) = x₁ (+) x₂ (+) ... (+) x_n That is, an XOR gate with n-inputs is the XOR of all the bits. This is not ambiguous because the XOR function is associative (all parenthesization of this expression are equivalent).

XNOR₂ gates

XNOR₂ gates have two bits of input and a single bit of output. The output of XNOR₂ gate is the negation of XOR₂ and has 1 when both inputs are the same.
If you look carefully at the drawing of the gate, there is a second arc behind the first one near the inputs. Since this second arc is hard to see, it's usually a good idea to write the word "XNOR" inside the gate.
The truth table defines the behavior of this gate.

x1	x0	z
0	0	0
0	1	1
1	0	1
1	1	0

The function implmented by XNOR₂ gates has interesting properties:

• The function is symmetric. Thus, x XNOR y == y XNOR x. This can be verified by using truth tables.
• The function is associative. Thus, (x XNOR y) XNOR z == x XNOR (y XNOR z). This can be verified by using truth tables.

Because of these properties, it's easy to define XNOR_n, which is an n-input XNOR gate. XNOR_n(x₁, x₂,...,x_n) = x₁ XNOR x₂ XNOR ... XNOR x_n That is, an XNOR gate with n-inputs is the XNOR of all the bits. This is not ambiguous because the XNOR function is associative (all parenthesization of this expression are equivalent).
(Error-checkers! You may wish to verify this, and email me if this is incorrect!).

Building Blocks

We can use logic gates to build circuits. While we've described 6 gates, you can do with only three gates to build all possible circuits: AND₂, OR₂, and NOT. In fact, you don't even need all three gates. It can be done in two kinds of gates of less. We'll explain in a future section. These circuits can implement any truth table.

Valid Combinational Circuits

The inverse is not true. Not every circuit that is built from gates corresponds to a truth table. In particular, you must observe the following rules if it's to correspond to a truth table.

• The output of a gate may only be attached to the input of another gate. (Think of this as a directed edge from output to input).
• There must be no cycles in the circuit. Treat the circuit like a directed graph with directed edges defined in the previous item.
• Although the output of a gate may be attached to more than one input, an input may not have two different outputs attached to it (this would create conflicting input signals).
• Each input of a gate must come from either the output of another gate or a source. A source is a source that generates either a 0 or 1.

Gate Delay

Real gates have delay. In other words, if you change the value of the inputs, say from 0 and 0 to 0 and 1, then the output takes some small amount of time before it changes. This delay is called gate delay. This delay is due to the fact that information can travel at most, the speed of light, and in reality, the time it takes to do the computation is not infinitely quick.
This delay limits how fast the inputs can change and yet the output have meaningful values. It also allows certain kinds of circuits to be created that don't follow the rules from the previous section. In particular, flip flops (to be discussed later) can be generated from gates that use cycles.

Why Subscripts?

Most books don't distinguish between an AND₂ gate and a AND₃ gate. They claim an AND gate is an AND gate, regardless of the number of inputs. While this is true, I subscript it because an AND₂ and an AND₃ do not have the same truth table. In particular, an AND₂ truth table has 4 rows while an AND₃ has 8. While the two truth tables are related, they still define different functions.
Thus, I make the distinction by subscripting the number of inputs.

Summary

Logic gates are the building blocks of combinational logic circuits. You can buy logic gates from electronic hobby places. These gates are primarily for hobbyists. Each chip usually has about 4 logic gates. Real computers don't use these kinds of gates, because they take far too much space. With VLSI technology, you can cram millions of gates onto a wafer no bigger that your thumbnail.
The behavior of logic gates can be described by truth tables. However, because these gates are "physical", they have some properties not expressed in truth tables. In particular, gate delay describes the amount of time it takes for the output to change when the input changes. This time is not zero, thus, one must wait a short amount of time for the output to take effect.
We'll discuss how to build circuits from these gates in a later set of notes.